LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY songer IS
PORT(clk12mhz: IN STD_LOGIC;
ENTITY songer IS
p>
clk8hz, done, COUT: IN STD_LOGIC;
code1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH1: OUT STD_LOGIC;
spkout: OUT STD_LOGIC);
END songer;
architecture one of songer is
COMPONENT notetabs
PORT (clk: IN STD_LOGIC ;
toneindex: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT tonetaba
PORT (done, COUT : in STD_LOGIC;
index: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
code: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
high: out STD_LOGIC;
tone: OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;
COMPONENT speakera
PORT (clk: IN STD_LOGIC ;
done, COUT: IN STD_LOGIC;
tone: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS: out STD_LOGIC);
END COMPONENT;
SIGNAL tone: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL toneindex: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1: notetabs PORT MAP(clk=gt; clk8hz, toneindex=gt; toneindex);
u2: tonetaba PORT MAP(index=gt; toneindex, tone=gt; tone, code= gt; code1, high=gt; high1, DONE=gt; DONE, cout=gt; cout);
u3: speaker PORT MAP (clk=gt; clk12mhz, done=gt; done, COUT= gt;COU
T,tone=gt;tone,spks=gt;spkout);
END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
END p>
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY notetabs IS
PORT(clk: IN STD_LOGIC;
toneindex: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE one OF notetabs IS
COMPONENT music
PORT(address: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clock: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
SIGNAL counter: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CNT8: PROCESS(clk, counter)
begin
IF counter =138 THEN counterlt;="00000000";
ELSIF(clk'EVENT AND clk='1')then
counterlt;=counter 1;
END IF;
END process;
END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tonetaba IS
PORT(done, COUT: in STD_LOGIC;
index: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
code: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
HIGH: OUT STD_LOGIC;
tone: OUT STD_LOGIC_VECTOR (10 DOWNTO 0));
END tonetaba;
architecture one OF tonetaba IS
BEGIN
search：PROCESS(index)
BEGIN
if done='1' OR COUT='1' THEN
CASE index IS
WHEN"0000"=gt;tonelt;="11111111111";codelt;="0000";highlt;='0 ';
WHEN"0001"=gt;tonelt;="011
00000101";codelt;="0001";highlt;='0';
WHEN"0010"=gt;tonelt;="01110010000";codelt;="0010";highlt;='0 ';
WHEN"0011"=gt;tonelt;="10000001100";codelt;="0011";highlt;='0';
WHEN"0101"=gt ;tonelt;="10010101101";codelt;="0101";highlt;='0';
WHEN"0110"=gt;tonelt;="10100001010";codelt;="0110"; highlt;='0';
WHEN"0111"=gt;tonelt;="10101011100";codelt;="0111"; highlt;='0';
WHEN "1000"=gt;tonelt;="10110000010";codelt;="0001";highlt;='1';
WHEN "1001"=gt;tonelt;="10111001000";codelt; ="0010"；highlt;='1';
WHEN"1010"=gt;tonelt;="11000000110";codelt;="0011";highlt;='1';
WHEN"1100"=gt;tonelt;="11001010110";codelt;="0101";highlt;='1';
WHEN"1101"=gt;tonelt;=" 11010000100";codelt;="0110";highlt;='1';
WHEN"1111"=gt;tonelt;="11011000000";codelt;="0001";highlt;='1 ';
WHEN OTHERS=gt;NULL;
END CASE;
END IF;
END PROCESS;
END ONE;
-CNC frequency converter
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY speaker IS
PORT( clk: IN STD_LOGIC;
done, COUT: IN STD_LOGIC;
tone: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS: OUT STD_LOGIC);
END speakera;
ARCHITECTURE one OF speakera is
SIGNAL preclk, fullspks: STD_LOGIC;
BEGIN
divideclk: pro
cess(clk)
VARIABLE count4: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF count4gt; 11 THEN
preclklt; ='1';
count4:="0000";
ELSIF clk'EVENT AND clk='1' THEN
count4:=count4 1; preclklt;='0';
END IF;
END PROCESS;
genspks: PROCESS(preclk, tone)
VARIABLE count11: STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
IF done='1'OR COUT='1' THEN
IF preclk'EVENT AND preclk ='1' THEN
IF count11=16#7FF# THEN count11:=tone;
fullspkslt;='1';
ELSE
count11:=count11 1;
fullspkslt;='0';
END IF;
END IF;
END IF;
END PROCESS;
delayspks: PROCESS(fullspks)
VARIABLE count2: STD_LOGIC;
BEGIN
IF fullspks'EVENT AND fullspks='1' then
count2：=NOT count2;
if count2='1' THEN spkslt;='1';
ELSE
spkslt;='0';
END IF;
END IF;
END PROCESS ;
END ONE;
Then customize a RAM yourself