CL is the abbreviation of CAS Latency, which is generally translated as CAS latency. It is a parameter when Northbridge (Intel)/CPU (AMD’s latest CPU) reads memory data. This parameter is important for the performance of the memory. It has a relatively large impact.

CAS is one of the memory signals. The specific process of reading memory is as follows: there are two signals: row (RAS#) and column (CAS#), similar to the rows of our graph paper and columns, when the memory data is to be read, the RAS# signal is pulled low. The address on the memory address line is the row address, which is equivalent to us determining the row on the graph paper. After a few clock cycles, the CAS# signal is pulled low, and the memory The address on the address line is the column address, which is equivalent to determining the column on the graph paper. In this way, the data of that grid on the graph paper can be determined. After a few clock cycles (CL), the corresponding memory reading will begin. Address data.

In this way, CL is the number of clocks from CAS# to start reading memory data. For memories with the same clock speed (such as DDR333), the smaller the CL, the faster the speed. However, for memories with different clock speeds, the smaller the CL, the faster the speed. Clock speed memory (such as DDR333 vs. DDR400), there is no comparison.

It’s a pity that you can’t post a picture, otherwise you can see it very intuitively.

Data output (read)

After selecting the column address, the specific storage unit has been determined, and the remaining thing is that the data passes through the data I/O channel (DQ) Output to the memory bus. However, after the CAS is issued, it still takes a certain period of time before data can be output. The period from the issuance of the CAS and read commands to the first data output is defined as CL (CAS Latency, CAS latency). Since CL only appears when reading, CL is also called read latency (RL, Read Latency). The unit of CL is the same as tRCD, which is the number of clock cycles. The specific time consumption is determined by the clock frequency.

However, CAS is not delivered to the storage unit after the CL cycle. In fact, CAS arrives instantly like RAS, but the response time of CAS is faster. Why? Assuming that the chip bit width is n bits and the number of columns is c, then a row address needs to gate n×c memory banks, and a column address only needs to gate n memory banks. However, the response time of the transistors in the memory bank will still make it impossible for the data to be triggered on the same rising edge as CAS, and must be delayed by at least one clock cycle.

The value of CL cannot exceed the design specifications of the chip, otherwise it will cause the memory to be unstable and even fail to boot (overclocking players should have experienced this), and it cannot be temporarily changed before data is read. The CL cycle is set in the MRS stage during the boot initialization process. Users are generally allowed to adjust it in the BIOS, and then the BIOS controls the Northbridge chip to change the information of the CL register in the MR through the A4-A6 address line during boot.

Reference material: Double Data Rate (DDR) SDRAM Specification