Xeon processor uses the same microstructure (microkernel) as the conventional desktop CPU, but pays more attention to the number of cores rather than the clock frequency, and adds advanced functions to servers and workstations, such as ECC memory, more cores, larger RAM and cache, and the exception handling mechanism of Machine Check Architecture (MCA) that provides enterprise-class reliability, availability and maintainability. In addition, some models also support QPI (Fast Channel Interconnection) and UPI (Super Channel Interconnection) buses, thus connecting multiple CPUs together, thus providing multi-channel processing capabilities such as 2-channel, 4-channel and 8-channel. .
There are currently six series of Xeon processors:
In addition, Xeon also includes Xeon Phi processors, and the latest Xeon Phi processors are based on Intel? Integrated many-core architecture (MIC architecture) can provide large-scale parallel processing and vectorization services for the most demanding high-performance computing applications, with a maximum of 72 cores and 36M L2 cache.
Multi-path interconnection technology is used to install multiple interconnected processors on a single motherboard, which mainly includes:
Many-core processor is a special multi-core processor designed for highly parallel processing. It does not pursue pipeline depth and hyper-threading to improve single-core performance, but contains a large number of simple and independent processor cores, so it has higher throughput or lower power consumption, but higher latency and lower single-thread performance.
Cache consistency is a difficulty to limit the expansion of multi-core processors. Many-core processors solve this problem through message passing, temporary memory, DMA, partitioned global address space (PGAS) and read-only/non-uniform cache. GPU can actually be regarded as a many-core processor with multiple shader processing units.
Multi-channel storage technology is a technology that can improve the transmission performance of stored data. By adding more parallel communication channels between DRAM and memory controller/chipset, the bandwidth of data transmission can be increased. Theoretically, with each additional channel, the data transmission performance will be doubled compared with a single channel. Generally speaking, multi-channel has requirements for memory specifications and slots, and multi-channel mode can only be enabled if the requirements are met.
At present, the most common multi-channel technology is dual-channel setting. For example, two sets of 64-bit DDR provide 128-bit DDR channels. Processors supporting quad-channel technology include Intel /AMD high-end processors, Cortex-A72 processors including ARM CoreLink CCI-500 technology, and high-end processors from Qualcomm and Samsung. Server processors such as AMD EPYC and Cavium ThunderX2 support eight-channel technology. In addition, the Haswell-EX architecture shown in Intel 20 12 also supports eight-channel DDR4.
Multithreading technology includes simultaneous multithreading (SMT) and time multithreading:
Temporal multithreading is also called cross multithreading, that is, one instruction is issued in one clock cycle, and multiple instructions of different threads are issued alternately. At present, multithreading only appears on barrel processors such as CDC 6000( 1960s), $ TerMTA (1988) and XMOS XCore XS 1(2007).
Hardware error detection and reporting mechanisms provided by Intel server processors include system bus errors, ECC errors, parity errors, cache errors, TLB errors, etc. , including a set of MSR registers for setting MCA and additional MSR registers for recording hardware errors.
Before the emergence of ECC technology, another error checking technology that was most used in memory was parity checking technology, which could only find errors but could not correct them.
ECC memory is enough to realize error checking and automatic error correction technology, which can automatically detect and correct the most common internal data damage, so that the system can run normally and will not be interrupted by errors. Under normal circumstances, ECC memory keeps the memory system free of single-bit errors, that is, 5-bit ECC code is used to correct 1 bit errors in 8-bit data. Every time the data bit doubles, the ECC only increases by 1 bit, that is, when the data bit is 16, the ECC bit is 6 bits, when the data bit is 32 bits, it is 7 bits, when the data bit is 64 bits, it is 8 bits, and so on.
Vector processing technology can directly manipulate one-dimensional arrays (vectors), which is just the opposite of scalar processing which can only process one data at a time. Vector processing technology can greatly improve performance in specific working environment, especially in numerical simulation or similar fields. Vector processing technology first appeared in the early 1970s and became the dominant direction of supercomputer design in 1970s and 1990s. Due to the rapid decline in the cost performance of conventional processor design, supercomputers based on vector processing gradually gave up their dominant position in the late 1990s. At present, most commercial CPU implementations can provide some form of vector processing instructions to process multiple vectorized data sets, which is called SIMD (single instruction multiple data). In addition, there is MIMD (Multiple Instruction Multiple Data) technology, which is used to process multi-directional quantized data sets with multiple instructions.