Diagnostic card code. Details

PCI/ISA dual-purpose DEBUG card fault code detailed list (only applicable to PCI/ISA dual-purpose and PCI single-purpose) Code Award BIOS AMI BIOS Phoenix and Tandy3000 BIOS]

00 (see special code meaning) The system configuration has been displayed; the control worker INT19 is about to be booted and loaded. (See special code meaning) (See special code meaning)

01 Processor test 1, processing status verification, if the test fails, the loop is infinite. Testing of processor registers is about to begin and non-maskable interrupts are about to be deactivated. CPU register test is in progress or failed.

02 Determine the type of diagnosis (normal or manufactured). The keyboard buffer will be invalidated if it contains data. Disable non-maskable interrupts; start with delay. CMOS write/read is in progress or failed.

03 Clear the 8042 keyboard controller and issue the TEST-KBRD command (AAH). Power-on delay completed. ROM B10S check component is in progress or malfunctioning.

04 Reset the 8042 keyboard controller and verify TESTKBRD. The keyboard controller is reset/power-on tested. Programmable interval timer test is in progress or failed.

05 If you continue to repeat manufacturing tests 1 to 5, you can obtain the 8042 control status. Soft reset/power-on confirmed; ROM boot is about to begin. DMA initial preparation is in progress or failed.

06 Initial preparation of the circuit chip, disabling video, parity, DMA circuit chip, and clearing the DMA circuit chip, all page registers and CMOS stop byte. Makes the initial preparation of the slice, disables video, parity, and DMA slices, and clears the DMA slice, all page registers, and the CMOS shutdown byte. Started ROM calculation of ROM BIOS check sum, as well as checking that the keyboard buffer is cleared. DMA initial page register read/write test is in progress or failed.

07 Processor test 2, verify the working of CPU registers. ROM BIOS checksum is OK, keyboard buffer cleared, issue BAT (Basic Assurance Test) command to keyboard. Meaningless

08 Make the CMOS timer make initial preparations and update the timer cycle normally. A BAT command has been issued to the keyboard and the BAT command is about to be written. RAM update check is in progress or failed.

09 EPROM checks the sum and must equal zero to pass. Verify the keyboard's basic assurance test, followed by verification of the keyboard command bytes. The first 64K RAM tests are underway.

0A makes initial preparations for the video interface. The keyboard command byte code is issued and the command byte data is about to be written. The first 64K RAM chip or data line failed and shifted. "

0B Test 8254 channel 0. Write the keyboard controller command byte, and the block/unlock command for pins 23 and 24 is about to be issued. The first 64K RAM odd/even logic fails.

0C Test 8054 channel 1. Keyboard controller pins 23 and 24 are blocked/unlocked; NOP command has been issued.

0D 1. Check the CPU. Whether the speed matches the system clock. 2. Check whether the programmed value of the control chip matches the initial setting. 3. If it fails, the NOP command has been processed; then test the first CMOS stop register. 64K RAM parity failure. S\

0E Test CMOS shutdown byte. CMOS shutdown register read/write test; CMOS checksum will be calculated (

0F Test extended CMOS.

Calculated CMOS checksum written to diagnostic byte; CMOS initial preparation begins. Meaningless. 0$;Pr

10 Test DMA channel 0. CMOS has been initially prepared, and the CMOS status register is about to be initially prepared for date and time. The first 64K RAM bit 0 failed.

11 Test DMA channel 1. The COMS status register has been initially prepared to disable the DMA and interrupt controller. The first 64K RAM bit 1 failed.

12 Test DMA page register. Disable DMA controller 1 and interrupt controllers 1 and 2; disable the video display and make port B initially ready. First 64K RAM bit 2 failed.

13 Test the 8471 keyboard controller interface. The video display is disabled and port B is initially prepared; chip initialization/memory auto-detection is about to begin. The first 64K RAM bit 3 failed. )

14 Test the memory update trigger circuit. Circuit chip initialization/memory automatic detection is completed; 8254 timer test is about to begin. First 64K RAM bit 4 failed.

15 Test the first 64K of system memory. Channel 2 timer is halfway tested; 8254 Channel 2 timer is about to complete testing. First 64K RAM bit 5 failed.

16 Create the interrupt vector table used by 8259. The 2nd channel timer test is over; the 8254 1st channel timer is about to complete the test. First 64K RAM bit 6 failed.

17 Adjust video input/output operation, enable video BIOS if installed. The timer test of channel 1 is over; the 8254 channel 0 is about to complete the test. First 64K RAM bit 7 failed.

18 Test the video memory. If the installation of the selected video BIOS passes, it can be bypassed. Channel 0 timer test is over; memory update is about to begin. The first 64K RAM bit 8 failed.

19 Test the interrupt controller (8259) mask bit of channel 1. The memory update has started and will be completed. First 64K RAM bit 9 failed.

1A Tests the mask bit of the interrupt controller (8259) of channel 2. Triggering memory update line, about to check 15 microsecond on/off time. The first 64K RAM bit 10 failed.

1B test mode CMOS battery level. Completed memory update time 30 microsecond test; basic 64K memory test is about to begin. The first 64K RAM bit 11 failed.

1C Test COMS check sum. Meaningless. The first 64K RAM bit 12 failed.

1D Set the configuration of COMS. Meaningless. The first 64K RAM bit 13 failed.

1E Determine the size of the system memory and compare the objective existence with the COMS value. Meaningless. The first 64K RAM bit 14 failed.

1F tests 64K memory to a maximum of 640K. Meaningless. First 64K RAM bit 15 failed.

20 Measure the fixed 8259 interrupt bit. Begins basic 64K memory test; will test address lines soon. Slave DMA register test is in progress or failed.

21 Maintains the non-maskable interrupt (NMI) bit (check for parity or input/output channels). Passes address line test; parity is about to be triggered. Main DMA register test is in progress or failed. )

22 Test the interrupt function of 8259. Ends triggering parity; will begin serial data read/write test. The main interrupt mask register is in progress or failed.

23 Test protection mode 8086 virtual mode and 8186 page mode.

Basic 64K serial data read/write test is OK; any conditioning before interrupt vector initialization is about to begin. The slave interrupt mask register test is in progress or failed.

24 Measures extended memory above 1Mb. Any adjustments prior to vector initialization are complete, and the initial preparation of the interrupt vector is about to begin. Set the ES segment address register registry to the high end of memory.

25 Test all memories except the first 64K. Completes initial preparation of interrupt vector; will start reading the 8042's input/output ports for rotating interrupts. Loading interrupt vector is in progress or failed.

26 Test exceptions to protection methods. Read and write the input/output port of the 8042; about to make initial preparations for global data to start rotating. Turn on the A20 address line; enable it to participate in addressing.

27 Determine the cache control or mask RAM. The initial preparation of all 1 data is complete; any initial preparation after the interrupt vector will then proceed. Keyboard controller test is in progress or failed.

28 Identify cache control or special 8042 keyboard controller. Initial preparation after interrupt vector completion; monochromatic Cantonese style is about to be set. CMOS power failure/checksum calculation in progress.

29 Meaningless. The monochrome mode has been set and the color mode will be set soon. Check of CMOS configuration validity is in progress.

2A Initializes the keyboard controller. The color mode has been set and the trigger parity before the ROM test is about to be performed. Empty 64K base memory.

2B Initial preparation of disk drives and controllers. Triggers parity end; any adjustments required before controlling the optional video ROM check. Screen memory test is in progress or failed.

2C Checks the serial port and makes initial preparations. Completed before video ROM control; about to view and control optional video ROMs. Screen initial preparation is in progress or failed.

2D checks the parallel serial port and makes initial preparations for it. To complete the optional video ROM control, control of any other processing after the video ROM recovery control is performed. The screen retrace test is in progress or failed.

2E Initial preparation of disk drives and controllers. Restore the processing after video ROM control; if EGA/VGA is not found, perform a display memory read and write test. Checking video ROM is in progress.

2F Detects the math coprocessor and makes initial preparations for it. No EGA/VGA found; display memory read/write test is about to begin. Meaningless.

30 Create basic memory and extended memory. Passes display memory read/write test; scan check is about to take place. Think the screen works.

31 Detect the selected ROM from C800:0 to EFFF:0 and prepare it for use. The display memory read/write test failed and another display memory read/write test is about to be performed. Monochrome monitors work.

32 Program the I/O chips such as COM/LTP/FDD/sound equipment on the motherboard to suit the setting values. Passed another display memory read/write test; another display scan check coming soon. Color monitors (40 columns) will work.

33 meaningless. The video monitor check is complete; it is time to verify the type of monitor using the adjustment switches and the actual plug-in card. Color monitors (80 columns) will work.

34 meaningless. The display adapter has been verified; display mode will be set next. Timer tick interrupt test is in progress or failed.

35 meaningless. Completed setting the display mode; about to check the BIOS ROM data area. Shutdown detection is in progress or failed.

36 meaningless. BIOS ROM data area checked; cursor for power-on information about to be set.

A-20 fails in the gate circuit.

37 meaningless. Cursor setting to identify power-on information has been completed; power-on information will be displayed. Unexpected interruption in protected mode.

38 Meaningless. Completed display of power-on information; new cursor position will be read out. RAM test is in progress or address failure > FFFFh.

39 Meaningless. The saved cursor position has been read out and the reference information string will be displayed. Meaningless.

3A is meaningless. The display of the reference information string ends; the discovery (ESC) information will be displayed soon. The display of the reference information string has ended; the discovery information will be displayed soon. Interval timer channel 2 tested or failed.

3B Use the OPT chip (486 only) to initially prepare the auxiliary cache. Discovery message displayed: Virtual mode, memory test is about to begin. The daily calendar clock test is in progress or out of order.

3C Establishes a flag that allows access to CMOS settings. Meaningless. The serial port test is in progress or failed.

3D Chunv Taiwanese keyboard/PS2 mouse/PNP device and total memory node. Meaningless. Parallel port test is in progress or failed.

3E Attempt to open L2 cache. Meaningless. The math processor test is in progress or failed.

3F meaningless. Meaningless. Meaningless.

40 meaningless. Preparations for virtual mode testing have begun; verification from video storage will be forthcoming. Adjust the CPU speed so that the peripheral clock matches exactly. 41 The interrupt is turned on, and the data will be initialized to facilitate 0:0 detection of memory changes (interrupt controller or memory bad). Restore from video memory after check; descriptor table ready. System plug-in board selection failed.

42 Display window to enter SETUP. Descriptor table is ready; virtual mode memory test is about to begin. Extended CMOS RAM failure.

43 If it is a plug-and-play BIOS, the serial port and parallel port are initialized. Enter virtual mode; interrupt for diagnostic mode is about to be implemented. Meaningless.

44 meaningless. Interrupt has been implemented (if the diagnostic switch is turned on; the data will be initially prepared to check the memory rollover at 0:0. BIOS interrupt is initialized.

45 Initialize the math processor. Data has been initially prepared ; About to check the memory rollover at 0:0 and find out the size of the system memory. )

46 Meaningless. Test memory has been returned; the memory size has been calculated and the page is about to be written to test the memory. Check the ROM version.

47 Meaningless. About to write a page in the extended memory; about to write a page in the basic 640K memory. Meaningless.

48 Meaningless. Base memory has been written to pages; 1Mb+ of memory will be finalized soon. Video check, CMOS reconfiguration. {J

49 Meaningless. Find the memory below 1Mb and check; the memory above 1Mb will be determined soon. Meaningless.

4A is meaningless. Find more than 1Mb of memory and check: The data area of ??BIOS ROM is about to be checked. Initialize the video.

4B is meaningless. The verification of the BIOS ROM data area is completed, and more than 1Mb of memory will be cleared for soft reset. Meaningless.

4C is meaningless. Clearing more than 1Mb of memory (soft reset) will clear more than 1Mb of memory. Block video BIOS ROM.

4D is meaningless. More than 1Mb of memory has been cleared (soft reset); the size of the memory will be saved. Meaningless.

4E If an error is detected, the error message will be displayed on the monitor and wait for the customer to press (F1) to continue.

Start memory test: (no soft reset); the first 64K memory test will be displayed. Display copyright information.

4F reads and writes soft and hard disk data and performs DOS boot. Starts displaying memory size, Testing Memory will update it; serial and random memory tests will be performed. Meaningless.

50 Store the CMOS value in the current BIOS temporary area into CMOS. Completed memory testing below 1Mb; sized high-speed memory for relocation and masking. Send CPU type and speed to the screen.

51 meaningless. Tests memory above 1Mb. Meaningless.

52 All ISA read-only memory ROMs are initialized, and finally allocate IRQ numbers to PCI and other initialization work. The memory test of more than 1Mb has been completed; it is about to return to real address mode. Enter keyboard detection.

53 If it is not a plug-and-play BIOS, initialize the serial port, parallel port and set the clock value. Save the size of CPU registers and memory and enter real address mode. Meaningless.

54 meaningless. The real address mode is successfully turned on; the registers saved when preparing to shut down will be restored. Scan the "strike key".

55 meaningless. The register has been restored and the address lines of gate A-20 will be disabled. Meaningless.

56 meaningless. Successfully disabled the A-20 address line; about to check the BIOS ROM data area. The keyboard test is over.

57 meaningless. The BIOS ROM data area is halfway checked; continue. Meaningless.

58 meaningless. BIOS ROM data area check completed; discovery information will be cleared. Non-setup interrupt testing.

59 meaningless. The message has been cleared; the message has been displayed; testing of the DMA and interrupt controller is about to begin. Meaningless.

5A is meaningless. Meaningless. Press "F2" key to set.

5B is meaningless. Meaningless. Test the basic memory address lines.

5C is meaningless. Meaningless. Testing 640K base memory.

5D is meaningless. Meaningless. Meaningless.

5E meaningless. Meaningless. Meaningless.

5F meaningless. Meaningless. Meaningless.

60 Set the hard disk boot sector virus protection function. Passed test of DMA page register; video memory is about to be verified. Test extended memory.

61 Display the system configuration table. The video memory check is completed; the test of the DMA#l basic register is about to be carried out. Meaningless.

62 Start system booting with interrupt 19H. Passed the test of DMA#l basic register; will soon conduct the test of DMA#2 register. Test the extended memory address lines.

63 meaningless. Passed the test of DMA#2 basic register; the BIOS ROM data area will be checked soon. Meaningless.

64 meaningless. The BIOS ROM data area has been checked halfway, continue. Meaningless.

65 meaningless. BIOS ROM data area check completed; DMA devices 1 and 2 will be programmed. Meaningless.

66 meaningless. Programming of DMA devices 1 and 2 is completed; interrupt controller No. 59 will be used for initial preparation. Cache registry is optimized and configured.

67 meaningless. 8259 Initial preparation is complete; keyboard testing is about to begin. Meaningless.

68 Meaningless. Meaningless. Make both external Cache and CPU internal Cache work.

69 meaningless. Meaningless. Meaningless.

6A is meaningless. Meaningless. Test and display external cache values.

6B is meaningless. Meaningless.

Meaningless.

6C is meaningless. Meaningless. Show blocked content.

6D is meaningless. Meaningless. Meaningless.

6E meaningless. Meaningless. Displays accessory configuration information.

6F is meaningless. Meaningless. Meaningless.

70 meaningless. Meaningless. Detected error codes are sent to the screen for display.

71 meaningless. Meaningless. Meaningless.

72 meaningless. Meaningless. Check whether there are any errors in the configuration.

73 meaningless. Meaningless. Meaningless.

74 meaningless. Meaningless. Test the real-time clock.

75 meaningless. Meaningless. Meaningless.

76 meaningless. Meaningless. Scan for keyboard errors.

77 meaningless. Meaningless. Meaningless.

78 meaningless. Meaningless. Meaningless.

79 meaningless. Meaningless. Meaningless.

7A is meaningless. Meaningless. Lock the keyboard.

7B is meaningless. Meaningless. Meaningless.

7C is meaningless. Meaningless. Set the hardware interrupt vector.

7D makes no sense. Meaningless. Meaningless.

7E meaningless. Meaningless. Tests whether the math processor is installed.

7F meaningless. Meaningless. Meaningless.

80 meaningless. The keyboard test has started, it is clearing and checking whether there are any stuck keys, and the keyboard is about to be restored. Turn off programmable input/output devices.

81 Meaningless. Find the incorrectly stuck key for keyboard recovery; a test command for the keyboard control port is about to be issued. Meaningless.

82 Meaningless. The keyboard controller interface test is completed, and the command bytes are written and the circular buffer is initially prepared. Detect and install fixed RS232 interface (serial port).

83 Meaningless. The command byte has been written, and the initial preparation of global data has been completed; it is about to check whether there is a key lock. Meaningless.

84 Meaningless. Checked for locked keys, about to check memory for CMOS mismatch. Detect and install fixed parallel ports.

85 Meaningless. Memory size checked; soft error and password or bypass arrangements will be displayed. Meaningless.

86 meaningless. Password checked: The bypass arrangement is about to be programmed. Reopen programmable I/O devices and detect fixed I/O conflicts.

87 Meaningless. After completing the programming before the arrangement, the programming of the CMOS arrangement will be performed. Meaningless.

88 Meaningless. Restore clear screen from CMOS scheduler; upcoming programming. Initialize the BIOS data area.

89 Meaningless. Post-arrangement programming is complete; the power-on screen message will be displayed. Meaningless.

8A makes no sense. Display the first screen information. Initialize the extended BIOS data area.

8B meaningless. The message: Main and video BIOS will be blocked soon. Meaningless.

8C Meaningless. Successfully disabling the main and video BIOS will initiate programming of the CMOS post-arrangement options. Perform floppy drive controller initialization.

8D makes no sense. Option programming has been scheduled followed by mouse inspection and initial preparation. Meaningless.

8E Meaningless. Checked the mouse slider and completed the initial preparation; the hard and floppy disks will be reset soon. Meaningless.

8F meaningless. The floppy disk has been checked. The disk will be initially prepared and then the floppy disk will be prepared. Meaningless.

90 meaningless. Soft disk configuration completed; hard disk presence will be tested. The hard disk controller is initialized.

91 meaningless. The hard disk existence test is completed; then configure the hard disk. Local bus hard disk controller initialization.

92 meaningless. Hard disk configuration is completed; the data area of ??BIOS ROM is about to be checked. Jump to user path 2.

93 meaningless. The data area of ??the BIOS ROM is half checked; continue. Meaningless.

94 meaningless. The data area of ??BIOS ROM has been checked, that is, the size of basic and extended memory has been set. Turn off the A20 address line.

95 meaningless. Adjusted memory size for mouse and hard disk type 47 support; display memory will be checked soon. Meaningless.

96 meaningless. Restore after checking the display memory; the initial preparation before C800:0 optional ROM control is about to begin. "ES segment" registry clearing.

97 meaningless. C800:0 Any initial preparation before optional ROM control is completed, followed by inspection and control of the optional ROM. Meaningless.

98 meaningless. Control of the option ROM is complete; any processing required after the option ROM returns control is about to occur. Find ROM selections.

99 meaningless. Any initial preparation required after the optional ROM test is complete; the data area for the timer or the printer base address is about to be established. Meaningless.

9A makes no sense. Return operation after setting the timer and printing the base address; the RS-232 base address is about to be set. Shield ROM selection.

9B meaningless. Returns after the RS-232 base address; initial preparations for coprocessor testing are about to begin. Meaningless.

9C meaningless. Required before coprocessor testing—initial preparation is complete; then the coprocessor is initially prepared. Establish power supply energy-saving management.

9D meaningless. The coprocessor is ready for initial preparation, and any initial preparation following the coprocessor test is about to take place. Meaningless.

9E meaningless. After completing the initial preparation of the coprocessor, the extended keyboard, keyboard identifier, and number lock will be checked. Open hardware interrupt.

9F meaningless. The extended keyboard has been checked, the identification flag is set, the digital lock is turned on or off, and a keyboard identification command will be issued. Meaningless.

A0 is meaningless. Issuing a keyboard recognition command: will restore the keyboard recognition flag. Set time and date.

A1 is meaningless. The keyboard identification flag is restored; the cache memory test is then performed. Meaningless.

A2 is meaningless. Cache test completed; any soft errors will be displayed. Check keypad lock.

A3 is meaningless. The soft error has been displayed; the keyboard strike rate is about to be set. Meaningless.

A4 is meaningless. After adjusting the keyboard's hitting rate, the waiting state of the memory will be established. Initialization of keyboard repeat input rate.

A5 is meaningless. The memory wait state is established; the screen is then cleared. Meaningless.

A6 is meaningless. Screen cleared; parity and non-maskable interrupts are about to be initiated. Meaningless.

A7 is meaningless. Non-maskable interrupts and parity are enabled; any initial preparations required to control the optional ROM at E000:0 are about to occur. Meaningless.

A8 is meaningless. The control ROM completes the initial preparation before E000:0 and will then control any initial preparation required at E000:0. Clear the "F2" key prompt.

A9 is meaningless. Returning from controlling the E000:0 ROM, any initial preparations required after controlling the E000:0 optional ROM will be made. Meaningless.

AA is meaningless. Initial preparation after controlling the optional ROM at E000:0 is complete; the system's configuration is about to be displayed.

Scan the "F2" key to hit.

AB is meaningless. Meaningless. Meaningless.

AC is meaningless. Meaningless. Go to settings.

AD is meaningless. Meaningless. Meaningless.

AE is meaningless. Meaningless. Clear the POST flag.

AF meaningless. Meaningless. Meaningless.

B0 is meaningless. Meaningless. Check for non-critical errors.

B1 is meaningless. Meaningless. Meaningless.

B2 is meaningless. Meaningless. The power-on self-test is completed and the system is ready to boot into the operating system.

B3 is meaningless. Meaningless. Meaningless.

B4 is meaningless. Meaningless. The buzzer sounds.

B5 is meaningless. Meaningless. Meaningless.

B6 is meaningless. Meaningless. Detect password settings (optional).

B7 is meaningless. Meaningless. Meaningless.

B8 is meaningless. Meaningless. Clear all description tables.

B9 is meaningless. Meaningless. Meaningless.

BA is meaningless. Meaningless. Meaningless.

BB is meaningless. Meaningless. Meaningless.

BC is meaningless. Meaningless. Clear the validation check value.

BD is meaningless. Meaningless. Meaningless.

BE program default values ??enter the control chip and conform to the modifiable binary default value table. Meaningless. Clear the screen (optional).

BF tests the CMOS establishment value. Meaningless. Detect viruses and prompt for data backup.

C0 initializes the cache. Meaningless. Try booting with interrupt 19.

C1 memory self-test. Meaningless. Look for the "55" "AA" mark in the boot sector.

C2 is meaningless. Meaningless. Meaningless.

C3 first 256K memory test. Meaningless. Meaningless.

C4 is meaningless. Meaningless. Meaningless.

C5 Copy BIOS from ROM for quick self-test. Meaningless. Meaningless.

C6 cache self-test. Meaningless. Meaningless.

C7 is meaningless. Meaningless. Meaningless.

C8 is meaningless. Meaningless. Meaningless.

C9 is meaningless. Meaningless. Meaningless.

CA detects the Micronies cache (if present) and makes initial preparations for it. Meaningless. Meaningless.

CB is meaningless. Meaningless. Meaningless.

CC shuts down the non-maskable interrupt handler. Meaningless. Meaningless.

CD is meaningless. Meaningless. Meaningless.

CE is meaningless. Meaningless. Meaningless.

CF is meaningless. Meaningless. Meaningless.

D0 is meaningless. Meaningless. Meaningless.

D1 is meaningless. Meaningless. Meaningless.

D2 is meaningless. Meaningless. Meaningless.

D3 is meaningless. Meaningless. Meaningless.

D4 is meaningless. Meaningless. Meaningless.

D5 is meaningless. Meaningless. Meaningless.

D6 is meaningless. Meaningless. Meaningless.

D7 is meaningless. Meaningless. Meaningless.

D8 is meaningless. Meaningless. Meaningless.

D9 is meaningless. Meaningless. Meaningless.

DA is meaningless. Meaningless. Meaningless.

DB is meaningless. Meaningless. Meaningless.

DC is meaningless. Meaningless. Meaningless.

DD is meaningless. Meaningless. Meaningless.

DE is meaningless. Meaningless. Meaningless.

DF is meaningless. Meaningless. Meaningless.

E0 is meaningless. Meaningless. Meaningless.

E1 is meaningless. Meaningless. Meaningless.

E2 is meaningless. Meaningless. Meaningless.

E3 is meaningless. Meaningless. Meaningless.

E4 is meaningless. Meaningless. Meaningless.

E5 is meaningless. Meaningless. Meaningless.

E6 is meaningless. Meaningless. Meaningless.

E7 meaningless. Meaningless. Meaningless.

E8 is meaningless. Meaningless. Meaningless.

E9 meaningless. Meaningless. Meaningless.

EA is meaningless. Meaningless. Meaningless.

EB is meaningless. Meaningless. Meaningless.

EC is meaningless. Meaningless. Meaningless.

ED is meaningless. Meaningless. Meaningless.

Unexpected exceptions for EE processors. Meaningless. Meaningless.

EF is meaningless. Meaningless. Meaningless.

F0 is meaningless. Meaningless. Meaningless.

F1 is meaningless. Meaningless. Meaningless.

F2 is meaningless. Meaningless. Meaningless.

F3 is meaningless. Meaningless. Meaningless.

F4 is meaningless. Meaningless. Meaningless.

F5 is meaningless. Meaningless. Meaningless.

F6 is meaningless. Meaningless. Meaningless.

F7 is meaningless. Meaningless. Meaningless.

F8 is meaningless. Meaningless. Meaningless.

F9 is meaningless. Meaningless. Meaningless.

FA is meaningless. Meaningless. Meaningless.

FB is meaningless. Meaningless. Meaningless.

FC is meaningless. Meaningless. Meaningless.

FD is meaningless. Meaningless. Meaningless.

FE is meaningless. Meaningless. Meaningless.

FF gives control of the INT19 bootloader and the motherboard is OK. (See the meaning of the special code) (See the meaning of the special code) (See the meaning of the special code) Lei Ao Extremely Cool Super Forum - Lei Ao Extremely Cool Super Forum, the latest software, BT downloads, games and entertainment, friends and chat, your online free paradise F0

Special codes "00", "FF" and other start codes appear in three situations:

1. "00" or "FF" appears after a series of other codes have appeared. ”, then the motherboard is OK.

2. If there are no errors in the CMOS settings, minor faults will not affect the continuation of the BIOS self-test, but "00" or "FF" will eventually appear.

3. If "00" or "FF" or other start code appears as soon as the computer is turned on and does not change, the motherboard is not running.