USB needs external PHY to connect with FPGA and firmware; ; Ethernet will not lose data before reaching TCP; PCI is gradually phased out, occupying more pins and limited bandwidth; SATA focuses on storage, and its protocol has high limitations. RapidIO is used in some occasions, which can realize a full mesh structure, but its development speed is slow in recent years.

PCIe has the following advantages:

A. high bandwidth. At present, there are PCIe Gen3 x 16 or PCIe Gen4x8 FPGAs, and the link speed can reach 128Gbps.

B.FPGA is directly connected without external PHY；;

C. The protocol ensures that the data transmission is correct, and the two-level CRC and retransmission mechanism ensure that the data is correct;

D. Rich software ecology, native support of various systems, and data interaction can be completed through simple driving;

E. protocols above PCIe are gradually increasing, such as NVMe is an upper layer protocol based on pcie;

Xilinx has been deeply involved in PCIe solutions since V4 series 15 years ago, providing many application-level solutions to help users focus on their own applications. In the early days, Xilinx provided application notes, such as XAPP859, XAPP 1052, etc. , which constructs the basic two-way data transmission. At that time, some third-party companies, similar to PLDA and NwLogic, also developed PCIe transmission scheme for Xilinx FPGA.